The present invention relates to digital data processing, and in particular to the design of chip interfaces for communicating data between an integrated circuit chip and other components of a digital data processing system.
In the latter half of the twentieth century, there began a phenomenon known as the information revolution. While the information revolution is a historical development broader in scope than any one event or machine, no single device has come to represent the information revolution more than the digital electronic computer. The development of computer systems has surely been a revolution. Each year, computer systems grow faster, store more data, and provide more applications to their users.
A modern computer system typically comprises a central processing unit (CPU) and supporting hardware necessary to store, retrieve and transfer information, such as communications buses and memory. It also includes hardware necessary to communicate with the outside world, such as input/output controllers or storage controllers, and devices attached thereto such as keyboards, monitors, tape drives, disk drives, communication lines coupled to a network, etc. The CPU is the heart of the system. It executes the instructions which comprise a computer program and directs the operation of the other system components.
From the standpoint of the computer""s hardware, most systems operate in fundamentally the same manner. Processors are capable of performing a limited set of very simple operations, such as arithmetic, logical comparisons, and movement of data from one location to another. But each operation is performed very quickly. Programs which direct a computer to perform massive numbers of these simple operations give the illusion that the computer is doing something sophisticated. What is perceived by the user as a new or improved capability of a computer system is made possible by performing essentially the same set of very simple operations, but doing it much faster. Therefore continuing improvements to computer systems require that these systems be made ever faster.
The overall speed of a computer system (also called the throughput) may be crudely measured as the number of operations performed per unit of time. Conceptually, the simplest of all possible improvements to system speed is to increase the clock speeds of the various components, and particularly the clock speed of the processor(s). E.g., if everything runs twice as fast but otherwise works in exactly the same manner, the system will perform a given task in half the time. Early computer processors, which were constructed from many discrete components, were susceptible to significant speed improvements by shrinking component size, reducing component number, and eventually, packaging the entire processor as an integrated circuit on a single chip. The reduced size made it possible to increase clock speed of the processor, and accordingly increase system speed.
Despite the enormous improvement in speed obtained from integrated circuitry, the demand for ever faster computer systems has continued. Hardware designers have been able to obtain still further improvements in speed by greater integration (i.e., increasing the number of circuits packed onto a single chip), by further reducing the size of circuits, and by various other techniques. For example, it has been possible to increase the width of various data buses to transfer more data with each bus cycle. Additional improvements have been made possible by increased parallelism, and specifically, by employing multiple processors. The modest cost of individual processors packaged on integrated circuit chips has made multi-processor systems practical, although such multiple processors add more layers of complexity to a system.
These various development trends in the design of computers and other digital data processing devices have had the effect of increasing the number of I/O pins on integrated circuit chips, and consequently, of increasing the number of data signal lines which communicate data from one chip to another.
Inter-chip communication lines are often arranged as buses having a defined protocol associated with a clock signal. To maximize overall system throughput, a fast clock is desirable, and designers are often pushing the envelope to obtain the fastest possible clock speed that the hardware will allow.
Where numerous inter-chip communication lines connect multiple ports on multiple chips, all simultaneously communicating data, various factors can degrade the signals received by a receiving chip. This degradation is not uniform. Each line has a different physical location on a circuit card or other carrier, it will lie adjacent a unique set of signal lines, and will have a unique driver circuit. It is therefore inevitable that some lines will exhibit a greater signal degradation, and will be more prone to soft (i.e., intermittent, non-repeatable) errors, than others.
In general, signal degradation may take the form of a phase shift, a voltage shift, or a purely random signal variation. A phase shift in the signal received by the receiving chip may be caused, e.g., by capacitance in the inter-chip signal line. Since each line has a different physical lay-out, the line capacitance (and the amount of phase shift) will vary with each line. A phase shift may also be caused by a clock skew within the transmitting chip, which again might vary from chip to chip. A voltage shift may be caused, e.g., by power variations in the transmitting chip""s drivers. Random variations in the signal have many possible causes too numerous to mention, but in general certain conditions make a line more susceptible to variation, such as the physical length of the line, the strength of the drivers etc. It will therefore be expected that some lines exhibit more random variation than others.
At some point, the clock signal regulating a chip-to-chip interface can be made to run slow enough so that variations in phase shift of the signal from line to line will not cause problems for the receiver. However, slowing the clock signal to accommodate the worst case signal line may adversely affect system throughput. As the number of signal lines increases, the variation of the worst case line is likely to be more extreme, requiring further slowing of the clock.
Recently, some chips have been designed with xe2x80x9celasticxe2x80x9d interfaces, in which the timing of the individual signal line receiver circuits can be varied to accommodate the individual variations in line capacitance and so forth. These elastic interfaces are typically tuned during the system design by measuring phase skew of the lines. Tuning elastic interfaces according to current techniques is a time-consuming process, which only promises to become more difficult as the number of inter-chip communication lines increases in future designs. Moreover, such tuning does not necessarily take other signal degrading factors into account, and does not necessarily obtain optimal results.
Historically, interfaces are often characterized and debugged in the development process using special test equipment, which is coupled to the signal lines to observe what is happening. As the number and density of lines increases, connecting test probes to individual lines is increasingly difficult and time consuming. Additionally, any test probe and attached testing apparatus has some finite impedance, which can distort the signal being characterized. When transmission errors are of an intermittent and infrequent nature, such conventional testing equipment is often inadequate to the task of characterizing the interface.
In order to design and produce systems of increased complexity, and in particular, having an increased number of inter-chip communication lines operating at high clock rates, it would be desirable to provide improved design techniques for inter-chip lines which overcome, tolerate, or otherwise accommodate individual line variations.
An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the interface between the two chips by separately generating identical pseudo-random test data at both the transmitting circuit and receiving circuit, comparing the data, and recording errors.
In the preferred embodiment, one or both of the receiving and transmitting circuits can be tuned on an individual line basis to reduce errors. Specifically, it is preferred that both the threshold voltage and the delay of the input signal may be adjusted at the receiver. Additionally, both the threshold voltage and delay of the clock signal regulating the interface may be adjusted at the receiver. Finally, the power and impedance of the driver may also be adjusted.
The receiver circuit preferably contains a counter for counting test cycles and a counter for counting error cycles, which can be masked for any particular line. The counters support testing a large number of cycles to accurately determine the bounds of an error curve at low error frequencies. Additional mask logic makes it possible to mask for 1""s or 0""s to determine which type of error is predominant.
A tunable and characterizable interface in accordance with the preferred embodiment of the present invention thus supports the accurate determination of low frequency intermittent error rates on an individual line basis for various tuning parameter settings. Characterization of an interface can be accomplished under realistic simulated operating conditions, in which line signals are not distorted by attached test probes and similar devices. System designers may therefore fine-tune the inter-chip interfaces on an individual line basis after the chips and circuit boards to which they are mounted have been designed and constructed. While the primary benefit is assumed to be understanding and tuning the interface in the system design phase, such capability could further be used to test and/or tune circuits during manufacturing to account for manufacturing variations, or even to test and/or tune circuits in the field to account for variations in operating environment, aging, and so forth.